The miniaturization of electrical components and their integration on a single piece of semiconductor material has been the catalyst for a world wide information revolution. As integrated circuit technology has progressed, it has been possible to store increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly and reliably. Central to this increased ability to store and retrieve data has been the dynamic random access memory, or DRAM, fabricated as an integrated circuit.
In the case of mass produced DRAMs, the cost per bit of memory has historically decreased as the number of bits which can be reliably stored on each integrated circuit has increased. Thus, it is advantageous to pack as many bit-storing memory cells as possible on each square unit of planar surface area available on a semiconductor integrated circuit.
DRAMs are formed of a large number of storage nodes which require transistors and capacitors in order to store information. The state of the art of fabricating the storage nodes of DRAM circuits has progressed to the point where the transistors of the nodes can be made much smaller than the capacitors.
In order to function properly within the nodes, the capacitors must possess a minimum amount of capacitance. If a capacitor exhibits too little capacitance, it loses the charge placed upon it too rapidly, causing errors in data storage. Thus, it is essential that the electrodes of storage node capacitors be large enough to retain an adequate charge in spite of parasitic capacitances and noise that may be present during circuit operation. Generally, it is desirable that each memory cell capacitor have as much capacitance as possible, but at least 20.times.10.sup.-15 farads, and preferably more than 60.times.10.sup.-15 farads of charge storage capacity.
The capacitance value, C, of a capacitor is dependent upon the dielectric constant, .epsilon., of the material placed between the electrodes of the capacitor, the distance, d, between the electrodes, and the effective surface area, A, of the electrodes. The relationship may be expressed C=A.epsilon./d. In many cases the material used as the dielectric between the electrodes of the capacitor is limited to only a few possibilities. Also, the minimum distance between the capacitor electrodes is generally limited to a particular value in order for the number of fabrication defects to be kept to an acceptably low value. Thus, the parameter which can most easily be varied to obtain increased storage capacity in DRAM capacitors is the surface area of the capacitor electrodes.
Therefore, it is a goal of DRAM designers to increase the surface area of capacitor electrodes as much as possible. It is also a goal to reduce the planar area occupied by each capacitor to a minimum so that as many memory cells as possible can be packed onto a single integrated circuit. Various three dimensional structures have been proposed and adopted in the art of DRAM fabrication to maintain the value of capacitors at a high level while keeping the planar area, or footprint, allocated to the capacitor at a minimum.
Among the proposed methods for maintaining cell capacitance while decreasing the planar area devoted to the cell capacitor is a "trench transistor cell," such as that described in Lu, "Advanced Structures for Dynamic RAMs", IEEE Circuits and Devices Magazine, pp. 27-35, (January 1989). In the trench transistor cell of the Lu paper, the capacitor cell is a vertical structure with an access transistor which is also vertical. The access transistor is placed above the cell capacitor. The described trench cell provides greater capacitor electrode area in a small planar area when compared to many planar capacitor structures. However, it provides only a modest increase in charge storage capacity, as well as additional difficulties during fabrication.
It is well known in the art that the storage capacitance of a node capacitor can be enhanced without increasing either the area required for the cell or the storage electrode height by "roughening" the silicon used to form a storage node electrode. In this method, a relatively flat silicon layer is subjected to surface migration and grain growth until the silicon layer forms into rounded clusters. An increase in capacitance results because the surface area of the rounded silicon clusters is greater than that of a relatively flat silicon layer. In this method (illustrated in FIGS. 1 and 2), one plate of the capacitor may be formed by initially depositing an amorphous silicon layer 20 on a dielectric layer 10. Next, the structure shown in FIG. 1 may be patterned and cleaned, and then subjected to an annealing process during which surface migration and grain growth of the amorphous silicon layer occurs. The surface migration and grain growth that occurs during the annealing step results in the formation of connected clusters 20a in the polysilicon layer 20, as shown in FIG. 2. The clustering shown in FIG. 2 serves to increase the surface area of the capacitor plate (thereby increasing the capacitance of the cell), while maintaining as constant the planar area devoted to the cell.
As an improvement to the process shown in FIG. 2, it would be desirable to further increase the surface area of the capacitor plate by annealing the polysilicon layer 20 until the clusters 20a grow to a size larger than that shown in FIG. 2. Unfortunately, such further annealing of the polysilicon layer 20 results in polysilicon clusters 20b that grow to a point at which they are no longer connected to each other (shown in FIG. 3). Once the polysilicon clusters 20b separate from each other, the polysilicon layer 20 no longer represents a single electrode and therefore has little utility as a capacitor plate.